Drain-induced barrier lowering

Drain-induced barrier lowering (DIBL) is a short-channel effect in MOSFETs referring originally to a reduction of threshold voltage of the transistor at higher drain voltages.wikipedia
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MOSFET

metal-oxide-semiconductorMOSMOS integrated circuit
Drain-induced barrier lowering (DIBL) is a short-channel effect in MOSFETs referring originally to a reduction of threshold voltage of the transistor at higher drain voltages.
In a long-channel device, there is no drain voltage dependence of the current once, but as channel length is reduced drain-induced barrier lowering introduces drain voltage dependence that depends in a complex way upon the device geometry (for example, the channel doping, the junction doping and so on).

Short-channel effect

Short channel effect
Drain-induced barrier lowering (DIBL) is a short-channel effect in MOSFETs referring originally to a reduction of threshold voltage of the transistor at higher drain voltages.
These effects include, in particular, drain-induced barrier lowering, velocity saturation, and hot carrier degradation.

Threshold voltage

gate voltagelow threshold voltagepinch-off voltage
Drain-induced barrier lowering (DIBL) is a short-channel effect in MOSFETs referring originally to a reduction of threshold voltage of the transistor at higher drain voltages. In a classic planar field-effect transistor with a long channel, the bottleneck in channel formation occurs far enough from the drain contact that it is electrostatically shielded from the drain by the combination of the substrate and gate, and so classically the threshold voltage was independent of drain voltage.
In wide planar transistors the threshold voltage is essentially independent of the drain–source voltage and is therefore a well defined characteristic, however it is less clear in modern nanometer-sized MOSFETs due to drain-induced barrier lowering.

Channel length modulation

channel pinchingchannel lengthchannel-length modulation
This increase is additional to the normal channel length modulation effect on output resistance, and cannot always be modeled as a threshold adjustment.
In the weak inversion region, the influence of the drain analogous to channel-length modulation leads to poorer device turn off behavior known as drain-induced barrier lowering, a drain induced lowering of threshold voltage.

Transistor

transistorstransistorizedsilicon transistor
Drain-induced barrier lowering (DIBL) is a short-channel effect in MOSFETs referring originally to a reduction of threshold voltage of the transistor at higher drain voltages.

Field-effect transistor

FETfield effect transistorfield-effect transistors
In a classic planar field-effect transistor with a long channel, the bottleneck in channel formation occurs far enough from the drain contact that it is electrostatically shielded from the drain by the combination of the substrate and gate, and so classically the threshold voltage was independent of drain voltage.

Depletion region

depletion layerinversion layerdepletion
The combined charge in the depletion region of the device and that in the channel of the device is balanced by three electrode charges: the gate, the source and the drain. As drain voltage is increased, the depletion region of the p-n junction between the drain and body increases in size and extends under the gate, so the drain assumes a greater portion of the burden of balancing depletion region charge, leaving a smaller burden for the gate.

P–n junction

p-n junctionreverse biasjunction
As drain voltage is increased, the depletion region of the p-n junction between the drain and body increases in size and extends under the gate, so the drain assumes a greater portion of the burden of balancing depletion region charge, leaving a smaller burden for the gate.

Subthreshold conduction

subthreshold leakagesubthreshold regionleakage
As channel length is reduced, the effects of DIBL in the subthreshold region (weak inversion) show up initially as a simple translation of the subthreshold current vs. gate bias curve with change in drain-voltage, which can be modeled as a simple change in threshold voltage with drain bias.

Reverse short-channel effect

To combat drain-induced barrier lowering (DIBL), MOSFET substrate near source and drain region are heavily doped (p+ in case of NMOS and n+ in case of PMOS) to reduce the width of the depletion region in the vicinity of source/substrate and drain/substrate junctions (called halo doping to describe the limitation of this heavy doping to the immediate vicinity of the junctions).