Input–output memory management unit

Comparison of the I/O memory management unit (IOMMU) to the memory management unit (MMU).

Input–output memory management unit is a memory management unit (MMU) that connects a direct-memory-access–capable (DMA-capable) I/O bus to the main memory.

- Input–output memory management unit

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Direct memory access

Feature of computer systems and allows certain hardware subsystems to access main system memory independently of the central processing unit (CPU).

Motherboard of a NeXTcube computer (1990). The two large integrated circuits below the middle of the image are the DMA controller (l.) and - unusual - an extra dedicated DMA controller (r.) for the magneto-optical disc used instead of a hard disk drive in the first series of this computer model.

Otherwise, the operating system would need to work around the problem by either using costly double buffers (DOS/Windows nomenclature) also known as bounce buffers (FreeBSD/Linux), or it could use an IOMMU to provide address translation services if one is present.

Graphics address remapping table

The graphics address remapping table (GART), also known as the graphics aperture remapping table, or graphics translation table (GTT), is an I/O memory management unit (IOMMU) used by Accelerated Graphics Port (AGP) and PCI Express (PCIe) graphics cards.

DMA attack

Type of side channel attack in computer security, in which an attacker can penetrate a computer or other device, by exploiting the presence of high-speed expansion ports that permit direct memory access .

An attempt to decode RSA key bits using power analysis. The left peak represents the CPU power variations during the step of the algorithm without multiplication, the right (broader) peak – step with multiplication, allowing an attacker to read bits 0, 1.

An IOMMU is a technology that applies the concept of virtual memory to such system busses, and can be used to close this security vulnerability (as well as increase system stability).

Host controller interface (USB, Firewire)

Register-level interface that enables a host controller for USB or IEEE 1394 hardware to communicate with a host controller driver in software.

Hardware interfaces of a Laptop computer: Ethernet network socket (center), to the left a part of the VGA port, to the right (upper) a display port socket, to the right (lower) a USB 2.0 socket.

It only supports 32-bit memory addressing, so it requires an IOMMU or a computationally expensive bounce buffer to work with a 64-bit operating system.

List of AMD Opteron processors

Name of a central processing unit family within the AMD64 line.

EDVAC, one of the first stored-program computers

All models support: MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, SSE4a, IOMMU, NX bit, AMD64, AMD-V, AES, CLMUL, AVX, CVT16–F16C, XOP, FMA4.

64-bit computing

In computer architecture, 64-bit integers, memory addresses, or other data units are those that are 64 bits wide.

Block diagram of a basic computer with uniprocessor CPU. Black lines indicate data flow, whereas red lines indicate control flow. Arrows indicate the direction of flow.

This problem is solved by having the OS take the memory restrictions of the device into account when generating requests to drivers for DMA, or by using an input–output memory management unit (IOMMU).

HP 9000

Line of workstation and server computer systems produced by the Hewlett-Packard Company.

Magnetic bubble memory board from early HP 9000/200 series computer

HP 9000 model 425 running HP-UX and Visual User Environment (VUE)

HP 9000 model 735 running the Common Desktop Environment (CDE) login manager

HP 9000 model 735 running HP-UX with CDE

HP 9000 model 712 running HP-UX with CDE

HP 9000 B180L displaying the CDE login manager

HP 9000 C360 displaying the CDE login manager

HP 9000 RP7410 system board with quad PA-RISC 8700+ CPUs

The I/O is unequal though; having one Ike IOMMU per bus means that one set of CPUs are closer to one set of I/O slots than the other.

Runway bus

Front-side bus developed by Hewlett-Packard for use by its PA-RISC microprocessor family.

Within a multi-core processor, the back-side bus is often internal, with front-side bus for external communication.

Most machines use the Runway bus to connect the CPUs directly to the IOMMU (Astro, U2/Uturn or Java) and memory.

Haswell (microarchitecture)

Codename for a processor microarchitecture developed by Intel as the "fourth-generation core" successor to the Ivy Bridge .

A Haswell wafer with several dies, with a pin for scale

Haswell featured a Fully Integrated Voltage Regulator.

Intel Haswell i7-4771 CPU, sitting atop its original packaging that contains an OEM fan-cooled heatsink

Intel VT-d, which is Intel's IOMMU, is supported on all i5 and i7 SKUs except the i5-4670K and i7-4770K. Support for VT-d requires the chipset and motherboard to also support VT-d.

AMD 800 chipset series

Set of chipsets developed by AMD, released in 2009.

The chipsets were supposed to support the codenamed "Montreal" processor made on 45 nm process, in Socket G3 package, supporting both unbuffered or buffered DDR3 (with Socket G3MX), HyperTransport 3.0 and IOMMU, all of them forming the codenamed "Piranha" server platform.