Memory management unit

MMUMMUsDAT boxBlock Address TranslationDAT (Dynamic Address Translation) boxdynamic address translationmemory managedmemory management cardmemory management unitsmemory protection
A memory management unit (MMU), sometimes called paged memory management unit (PMMU), is a computer hardware unit having all memory references passed through itself, primarily performing the translation of virtual memory addresses to physical addresses.wikipedia
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Virtual memory

virtual storagememoryswap
An MMU effectively performs virtual memory management, handling at the same time memory protection, cache control, bus arbitration and, in simpler computer architectures (especially 8-bit systems), bank switching.
Address translation hardware in the CPU, often referred to as a memory management unit or MMU, automatically translates virtual addresses to physical addresses.

CPU cache

cachecache memorycaches
An MMU effectively performs virtual memory management, handling at the same time memory protection, cache control, bus arbitration and, in simpler computer architectures (especially 8-bit systems), bank switching.
Other types of caches exist (that are not counted towards the "cache size" of the most important caches mentioned above), such as the translation lookaside buffer (TLB) that is part of the memory management unit (MMU) that most CPUs have.

Translation lookaside buffer

TLBprocess-context identifierTLBs
An associative cache of PTEs is called a translation lookaside buffer (TLB) and is used to avoid the necessity of accessing the main memory every time a virtual address is mapped.
It is a part of the chip’s memory-management unit (MMU).

Physical address

addressbinary addressmemory physical address
A memory management unit (MMU), sometimes called paged memory management unit (PMMU), is a computer hardware unit having all memory references passed through itself, primarily performing the translation of virtual memory addresses to physical addresses.
In particular, in computers utilizing a memory management unit (MMU) to translate memory addresses, the virtual and physical addresses refer to an address before and after translation performed by the MMU, respectively.

Page fault

invalid page faultmemory exceptionminor page fault
In this case, the MMU signals a page fault to the CPU. The MMU may also generate illegal access error conditions or invalid page faults upon illegal or non-existing memory accesses, respectively, leading to segmentation fault or bus error conditions when handled by the operating system.
A page fault (sometimes called #PF, PF or hard fault) is a type of exception raised by computer hardware when a running program accesses a memory page that is not currently mapped by the memory management unit (MMU) into the virtual address space of a process.

Cache (computing)

cachecachingcached
A PTE may also include information about whether the page has been written to (the "dirty bit"), when it was last used (the "accessed bit," for a least recently used (LRU) page replacement algorithm), what kind of processes (user mode or supervisor mode) may read and write it, and whether it should be cached.
Examples of caches with a specific function are the D-cache and I-cache and the translation lookaside buffer for the MMU.

Motorola 68851

68851MC68851
In some early microprocessor designs, memory management was performed by a separate integrated circuit such as the VLSI VI475 (1986), the Motorola 68851 (1984) used with the Motorola 68020 CPU in the Macintosh II, or the Z8015 (1985) used with the Zilog Z8000 family of processors.
The Motorola 68851 is an external Memory Management Unit (MMU) which is designed to provide paged memory support for the 68020 using that processor's coprocessor interface.

Zilog Z280

Z280
Later microprocessors (such as the Motorola 68030 and the Zilog Z280) placed the MMU together with the CPU on the same integrated circuit, as did the Intel 80286 and later x86 microprocessors.
Zilog added a memory management unit (MMU) to expand the addressing range to 16 MB, features for multitasking and multiprocessor and coprocessor configurations, a 256-byte cache, and a huge number of new instructions and addressing modes (giving a total of over 2000 combinations).

Motorola 68030

6803068EC03068030 CPU
Later microprocessors (such as the Motorola 68030 and the Zilog Z280) placed the MMU together with the CPU on the same integrated circuit, as did the Intel 80286 and later x86 microprocessors.
It also has an on-chip memory management unit (MMU) but does not have a built in floating-point unit (FPU).

Bus error

busBus Errorsunaligned addresses
The MMU may also generate illegal access error conditions or invalid page faults upon illegal or non-existing memory accesses, respectively, leading to segmentation fault or bus error conditions when handled by the operating system.
Trying to access an undefined virtual memory address is generally considered to be a segmentation fault rather than a bus error, though if the MMU is separate, the processor cannot tell the difference.

Segmentation fault

segmentation violationaccess violationsegfault
The MMU may also generate illegal access error conditions or invalid page faults upon illegal or non-existing memory accesses, respectively, leading to segmentation fault or bus error conditions when handled by the operating system.
At the hardware level, the fault is initially raised by the memory management unit (MMU) on illegal access (if the referenced memory exists), as part of its memory protection feature, or an invalid page fault (if the referenced memory does not exist).

IBM System/360 Model 67

Model 67360/67S/360-67
The IBM System/360 Model 67, which was introduced Aug. 1965, included an MMU that was called a dynamic address translation (DAT) box.
Unlike the rest of the S/360 series, it included features to facilitate time-sharing applications, notably a DAT box to support virtual memory and 32-bit addressing.

Kernel (operating system)

kerneloperating system kernelkernels
P1 space: (Or control space) which is also per-process and is typically used for supervisor, executive, kernel, user stacks and other per-process control structures managed by the operating system.
An efficient and simple way to provide hardware support of capabilities is to delegate to the MMU the responsibility of checking access-rights for every memory access, a mechanism called capability-based addressing.

Bank switching

bank-switchingbank-switchedbank switched
An MMU effectively performs virtual memory management, handling at the same time memory protection, cache control, bus arbitration and, in simpler computer architectures (especially 8-bit systems), bank switching.
Bank switching was later supplanted by segmentation in many 16-bit systems, which in turn gave way to paging memory management units.

Microprocessor

microprocessorsprocessorchip
In some early microprocessor designs, memory management was performed by a separate integrated circuit such as the VLSI VI475 (1986), the Motorola 68851 (1984) used with the Motorola 68020 CPU in the Macintosh II, or the Z8015 (1985) used with the Zilog Z8000 family of processors.
The 8086 and successors had an innovative but limited method of memory segmentation, while the 80286 introduced a full-featured segmented memory management unit (MMU).

Intel 80286

80286286Intel 286
Later microprocessors (such as the Motorola 68030 and the Zilog Z280) placed the MMU together with the CPU on the same integrated circuit, as did the Intel 80286 and later x86 microprocessors.
In addition, it was the first commercially available microprocessor with on-chip MMU capabilities (systems using the contemporaneous Motorola 68010 and NS320xx could be equipped with an optional MMU controller).

Zilog Z8000

Z8000Zilog Z8001Zilog Z8002
In some early microprocessor designs, memory management was performed by a separate integrated circuit such as the VLSI VI475 (1986), the Motorola 68851 (1984) used with the Motorola 68020 CPU in the Macintosh II, or the Z8015 (1985) used with the Zilog Z8000 family of processors.
The onchip MMU reduced manufacturing cost by eliminating the need for additional support circuitry required to support virtual memory.

Linux

GNU/LinuxLinLinux operating system
For example, Linux on VAX groups eight pages together.
Specialized distributions and kernel forks exist for less mainstream architectures; for example, the ELKS kernel fork can run on Intel 8086 or Intel 80286 16-bit microprocessors, while the µClinux kernel fork may run on systems without a memory management unit.

VAX

DEC VAXVAX 11/780DEC VAX ULTRIX
VAX pages are 512 bytes, which is very small.
The 78032 was the first microprocessor with an on-board memory management unit The MicroVAX II was based on a single, quad-sized processor board which carried the processor chips and ran the MicroVMS or Ultrix-32 operating systems.

Memory segmentation

segmentationsegmentmemory segment
While this article concentrates on modern MMUs, commonly based on pages, early systems used a similar concept for base-limit addressing that further developed into segmentation.
A hardware memory management unit (MMU) is responsible for translating the segment and offset into a physical address, and for performing checks to make sure the translation can be done and that the reference to that segment and offset is permitted.

ARM architecture

ARMNEONARMv7
ARM architecture-based application processors implement an MMU defined by ARM's virtual memory system architecture.
The coprocessor space is divided logically into 16 coprocessors with numbers from 0 to 15, coprocessor 15 (cp15) being reserved for some typical control functions like managing the caches and MMU operation on processors that have one.

Page table

page table entriespage table entryinverted page table
Most MMUs use an in-memory table of items called a "page table", containing one "page table entry" (PTE) per page, to map virtual page numbers to physical page numbers in main memory.
The CPU's memory management unit (MMU) stores a cache of recently used mappings from the operating system's page table.

PowerPC

PPCbelowIBM PowerPC
In PowerPC G1, G2, G3, and G4 pages are normally 4 KB.
A paged memory management architecture that is used extensively in server and PC systems.

Macintosh II

Mac IIIIMac-II
In some early microprocessor designs, memory management was performed by a separate integrated circuit such as the VLSI VI475 (1986), the Motorola 68851 (1984) used with the Motorola 68020 CPU in the Macintosh II, or the Z8015 (1985) used with the Zilog Z8000 family of processors.
All systems included a mouse and a single 800 KB 3.5" floppy disk drive; a 68551 PMMU was available as an option.

Sun-1

The original Sun 1 was a single-board computer built around the Motorola 68000 microprocessor and introduced in 1982.
It combined a 10 MHz Motorola 68000 microprocessor, a Sun designed memory management unit (MMU), 256 KB of zero wait state memory with parity, up to 32 KB of EPROM memory, two serial ports, a 16-bit parallel port and an Intel Multibus (IEEE 796 bus) interface in a single 12 in, 6.75 in Multibus form factor.