Memory management unit

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Schematic of the operation of an MMU
VLSI VI475 MMU "Apple HMMU" from the Macintosh II used with the Motorola 68020
Heterogeneous System Architecture (HSA) creates a unified virtual address space for CPUs, GPUs and DSPs, obsoleting the mapping tricks and data copying.

Computer hardware unit having all memory references passed through itself, primarily performing the translation of virtual memory addresses to physical addresses.

- Memory management unit
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General working of TLB

Translation lookaside buffer

Memory cache that stores the recent translations of virtual memory to physical memory.

Memory cache that stores the recent translations of virtual memory to physical memory.

General working of TLB
Flowchart shows the working of a translation lookaside buffer. For simplicity, the page-fault routine is not mentioned.

It is a part of the chip's memory-management unit (MMU).

Diagram of relationship between the virtual and physical address spaces

Physical address

Memory address that is represented in the form of a binary number on the address bus circuitry in order to enable the data bus to access a particular storage cell of main memory, or a register of memory-mapped I/O device.

Memory address that is represented in the form of a binary number on the address bus circuitry in order to enable the data bus to access a particular storage cell of main memory, or a register of memory-mapped I/O device.

Diagram of relationship between the virtual and physical address spaces

In particular, in computers utilizing a memory management unit (MMU) to translate memory addresses, the virtual and physical addresses refer to an address before and after translation performed by the MMU, respectively.

Diagram of a CPU memory cache operation

Cache (computing)

Hardware or software component that stores data so that future requests for that data can be served faster; the data stored in a cache might be the result of an earlier computation or a copy of data stored elsewhere.

Hardware or software component that stores data so that future requests for that data can be served faster; the data stored in a cache might be the result of an earlier computation or a copy of data stored elsewhere.

Diagram of a CPU memory cache operation
A write-through cache with no-write allocation
A write-back cache with write allocation

Examples of caches with a specific function are the D-cache and I-cache and the translation lookaside buffer for the MMU.

An Intel i386DX 16 MHz processor with a gray ceramic heat spreader.

I386

32-bit microprocessor introduced in 1985.

32-bit microprocessor introduced in 1985.

An Intel i386DX 16 MHz processor with a gray ceramic heat spreader.
Intel A80386DX-20 CPU die image
Block diagram of the i386 microarchitecture
A surface-mount version of Intel 80386SX processor in a Compaq Deskpro computer. It is non-upgradable unless hot-air circuit-board rework is performed
Die of Intel 80386SX
i386SL from 1990
Intel i386 packaged by IBM
Typical 386 upgrade CPUs from Cyrix and Texas Instruments
Intel i386DX, 25 MHz
80386SX 16 MHz
Intel i386EXTC, 25 MHz
Intel i386CXSA, 25 MHz
A very early 80386 at 12 MHz (A80386-12), before the 32-bit multiply bug was found
An A80386-16 marked "16 BIT S/W ONLY" with the multiply bug
A bug-free A80386-16 marked "ΣΣ"

The 80386 added a three-stage instruction pipeline which it brings up to total of 6-stage instruction pipeline, extended the architecture from 16-bits to 32-bits, and added an on-chip memory management unit.

An Intel A80286-8 processor with a gray ceramic heat spreader

Intel 80286

16-bit microprocessor that was introduced on February 1, 1982.

16-bit microprocessor that was introduced on February 1, 1982.

An Intel A80286-8 processor with a gray ceramic heat spreader
AMD 80286 (16 MHz version)
Simplified 80286 microarchitecture
Intel 80286 die
Siemens 80286 (10 MHz version)
IBM 80286 (8 MHz version)

In addition, it was the first commercially available microprocessor with on-chip MMU capabilities (systems using the contemporaneous Motorola 68010 and NS320xx could be equipped with an optional MMU controller).

Computer simulation, one of the main cross-computing methodologies.

Page fault

Computer simulation, one of the main cross-computing methodologies.

In computing, a page fault (sometimes called PF or hard fault) is an exception that the memory management unit (MMU) raises when a process accesses a memory page without proper preparations.

Virtual memory combines active RAM and inactive memory on DASD to form a large range of contiguous addresses.

Virtual memory

Memory management technique that provides an "idealized abstraction of the storage resources that are actually available on a given machine" which "creates the illusion to users of a very large memory".

Memory management technique that provides an "idealized abstraction of the storage resources that are actually available on a given machine" which "creates the illusion to users of a very large memory".

Virtual memory combines active RAM and inactive memory on DASD to form a large range of contiguous addresses.
The University of Manchester Atlas Computer was the first computer to feature true virtual memory.

Address translation hardware in the CPU, often referred to as a memory management unit (MMU), automatically translates virtual addresses to physical addresses.

Motherboard of a NeXTcube computer (1990). At the lower edge of the image left from the middle, there is the CPU Motorola 68040 operated at 25 MHz with two separate level 1 caches of 4 KiB each on the chip, one for the instructions and one for data. The board has no external L2 cache.

CPU cache

Hardware cache used by the central processing unit of a computer to reduce the average cost (time or energy) to access data from the main memory.

Hardware cache used by the central processing unit of a computer to reduce the average cost (time or energy) to access data from the main memory.

Motherboard of a NeXTcube computer (1990). At the lower edge of the image left from the middle, there is the CPU Motorola 68040 operated at 25 MHz with two separate level 1 caches of 4 KiB each on the chip, one for the instructions and one for data. The board has no external L2 cache.
An illustration of different ways in which memory locations can be cached by particular cache locations
Memory hierarchy of an AMD Bulldozer server
Cache hierarchy of the K8 core in the AMD Athlon 64 CPU.
Read path for a 2-way associative cache

Other types of caches exist (that are not counted towards the "cache size" of the most important caches mentioned above), such as the translation lookaside buffer (TLB) which is part of the memory management unit (MMU) which most CPUs have.

Motorola 68030 microprocessor

Motorola 68030

32-bit microprocessor in the Motorola 68000 family.

32-bit microprocessor in the Motorola 68000 family.

Motorola 68030 microprocessor
Motorola MC68030RC33B die

The 68030 is essentially a 68020 with a memory management unit (MMU) and instruction and data caches of 256 bytes each.

Relationship between pages addressed by virtual addresses and the pages in physical memory, within a simple address space scheme. Physical memory can contain pages belonging to many processes. Pages can be held on disk if seldom used, or if physical memory is full. In the diagram above, some pages are not in physical memory.

Page table

Data structure used by a virtual memory system in a computer operating system to store the mapping between virtual addresses and physical addresses.

Data structure used by a virtual memory system in a computer operating system to store the mapping between virtual addresses and physical addresses.

Relationship between pages addressed by virtual addresses and the pages in physical memory, within a simple address space scheme. Physical memory can contain pages belonging to many processes. Pages can be held on disk if seldom used, or if physical memory is full. In the diagram above, some pages are not in physical memory.
Actions taken upon a virtual to physical address translation. Each translation is restarted if a TLB miss occurs, so that the lookup can occur correctly through hardware.
Two-level page table structure in x86 architecture (without PAE or PSE).
Three-level page table structure in x86 architecture (with PAE, without PSE).

The memory management unit (MMU) inside the CPU stores a cache of recently used mappings from the operating system's page table.