PHY (chip)

PHYPHY chipEthernet PHYPHYceiverPHYsPHY (Physical layer)PHY LayerPHY transceiversphysicalphysical layer
A PHY, an abbreviation for "physical layer", is an electronic circuit, usually implemented as a chip, required to implement physical layer functions of the OSI model.wikipedia
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Physical layer

physicalLayer 1PHY
A PHY, an abbreviation for "physical layer", is an electronic circuit, usually implemented as a chip, required to implement physical layer functions of the OSI model.
This layer may be implemented by a PHY chip.

Media-independent interface

Media Independent InterfaceGMIIMII
It is usually with a Media Independent Interface (MII) interfaced to a MAC chip in a microcontroller or other system that takes care of the higher layer functions. More specifically, the Ethernet PHY is a chip that implements the hardware send and receive function of Ethernet frames; it interfaces between the analog domain of Ethernet's line modulation and the digital domain of link-layer packet signaling.
The media-independent interface (MII) was originally defined as a standard interface to connect a Fast Ethernet (i.e., 100 Mbit/s) media access control (MAC) block to a PHY chip.

Physical Medium Dependent

Physical Layer Medium DependentPMD
A PHY device typically includes both Physical Coding Sublayer (PCS) and Physical Medium Dependent (PMD) layer functionality.

Microsemi

Microsemi Corporationacquiredmicrosemiconductor
Examples include the Microsemi SimpliPHY and SynchroPHY VSC82xx/84xx/85xx/86xx family, Marvell Alaska 88E1310/88E1310S/88E1318/88E1318S Gigabit Ethernet transceivers and offerings from Intel and ICS.

Wireless LAN

WLANwireless local area networkwireless
Neither European standard achieved the commercial success of 802.11, although much of the work on HiperLAN/2 has survived in the physical specification (PHY) for IEEE 802.11a, which is nearly identical to the PHY of HiperLAN/2.

Medium access control

media access controlMACMAC layer
A PHY connects a link layer device (often called MAC as an acronym for medium access control) to a physical medium such as an optical fiber or copper cable.
In turn, the medium access control block is formally connected to the PHY via a media-independent interface.

Ethernet

Ethernet portEthernet cableEthernet network
A PHY chip (PHYceiver) is commonly found on Ethernet devices.

Electronic circuit

circuitcircuitryelectronic circuits
A PHY, an abbreviation for "physical layer", is an electronic circuit, usually implemented as a chip, required to implement physical layer functions of the OSI model.

Integrated circuit

integrated circuitsmicrochipchip
A PHY, an abbreviation for "physical layer", is an electronic circuit, usually implemented as a chip, required to implement physical layer functions of the OSI model.

OSI model

OSIOpen Systems InterconnectionOSI reference model
A PHY, an abbreviation for "physical layer", is an electronic circuit, usually implemented as a chip, required to implement physical layer functions of the OSI model.

Link layer

Linklink protocollink-layer
A PHY connects a link layer device (often called MAC as an acronym for medium access control) to a physical medium such as an optical fiber or copper cable.

Optical fiber

fiber opticfiber opticsfiber-optic
A PHY connects a link layer device (often called MAC as an acronym for medium access control) to a physical medium such as an optical fiber or copper cable.

Copper conductor

copper wirecoppercopper cable
A PHY connects a link layer device (often called MAC as an acronym for medium access control) to a physical medium such as an optical fiber or copper cable.

Physical Coding Sublayer

Physical Medium AttachmentPCS code
A PHY device typically includes both Physical Coding Sublayer (PCS) and Physical Medium Dependent (PMD) layer functionality.

Microcontroller

microcontrollersMCUmicro-controller
It is usually with a Media Independent Interface (MII) interfaced to a MAC chip in a microcontroller or other system that takes care of the higher layer functions.

Frame (networking)

frameframesdata frame
More specifically, the Ethernet PHY is a chip that implements the hardware send and receive function of Ethernet frames; it interfaces between the analog domain of Ethernet's line modulation and the digital domain of link-layer packet signaling.

Data link layer

Layer 2Data linkLayer-2
The PHY usually does not handle MAC addressing, as that is the link layer's job.

Wake-on-LAN

Wake on LANWoLwake-up-packet
Similarly, Wake-on-LAN and Boot ROM functionality is implemented in the network interface card (NIC), which may have PHY, MAC, and other functionality integrated into one chip or as separate chips.

Network booting

network bootnetbootBoot ROM
Similarly, Wake-on-LAN and Boot ROM functionality is implemented in the network interface card (NIC), which may have PHY, MAC, and other functionality integrated into one chip or as separate chips.

Network interface controller

network cardnetwork interface cardnetwork adapter
Similarly, Wake-on-LAN and Boot ROM functionality is implemented in the network interface card (NIC), which may have PHY, MAC, and other functionality integrated into one chip or as separate chips.

Marvell Technology Group

MarvellMarvell SemiconductorMarvell Technology
Examples include the Microsemi SimpliPHY and SynchroPHY VSC82xx/84xx/85xx/86xx family, Marvell Alaska 88E1310/88E1310S/88E1318/88E1318S Gigabit Ethernet transceivers and offerings from Intel and ICS.