X86 instruction listings

The x86 architectures were based on the Intel 8086 microprocessor chip, initially released in 1978.

The x86 instruction set refers to the set of instructions that x86-compatible microprocessors support.

- X86 instruction listings

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Instruction set architecture

Instruction set architecture , also called computer architecture, is an abstract model of a computer.

One instruction may have several fields, which identify the logical operation, and may also include source and destination addresses and constant values. This is the MIPS "Add Immediate" instruction, which allows selection of source and destination registers and inclusion of a small constant.

For example, the Intel Pentium and the AMD Athlon implement nearly identical versions of the x86 instruction set, but they have radically different internal designs.

P6 (microarchitecture)

Sixth-generation Intel x86 microarchitecture, implemented by the Pentium Pro microprocessor that was introduced in November 1995.

Die shot of Deschutes core

CMOV instructions, which are heavily used in compiler optimization.

X86 assembly language

Name for the family of assembly languages which provide some level of backward compatibility with CPUs back to the Intel 8008 microprocessor, which was launched in April 1972.

The x86 registers can be used by using the MOV instructions.

Transmeta Crusoe

Family of x86-compatible microprocessors developed by Transmeta and introduced in 2000.

A Transmeta Crusoe
Photo of CPUID for Transmeta Crusoe TM5800 800Mhz on Fujitsu P2040
A Transmeta CPU from a Fujitsu Lifebook P series laptop

This is used to allow the microprocessors to emulate the Intel x86 instruction set.

Shellcode

Small piece of code used as the payload in the exploitation of a software vulnerability.

Bruce Sterling, author of The Hacker Crackdown

B8 01000000 MOV EAX,1 // Set the register EAX to 0x000000001

Prefetching

Technique for speeding up fetch operations by beginning a fetch operation whose result is expected to be needed soon.

400x400px

, an X86 instruction in computing

SSE2

One of the Intel SIMD (Single Instruction, Multiple Data) processor supplementary instruction sets first introduced by Intel with the initial version of the Pentium 4 in 2000.

Single instruction, multiple data

SSE2 is an extension of the IA-32 architecture, based on the x86 instruction set.

Intel 8087

The first x87 floating-point coprocessor for the 8086 line of microprocessors.

Intel 8087 math coprocessor
Die of Intel 8087
Simplified 8087 microarchitecture
Intel 8087 math coprocessor pinout
The original 5 MHz Intel D8087
An 8 MHz Intel D8087-2
An Intel 4 MHz C8087-3

It worked in tandem with the 8086 or 8088 and introduced about 60 new instructions.

Linearizability

Operation is linearizable if it consists of an ordered list of invocation and response events (event), that may be extended by adding response events such that:

In grey a linear sub-history, processes beginning in b do not have a linearizable history because b0 or b1 may complete in either order before b2 occurs.

atomic swap (the RDLK instruction in some Burroughs mainframes, and the XCHG x86 instruction);

Test register

Register used by the processor, usually to do a self-test.

An Intel i386DX 16 MHz processor with a gray ceramic heat spreader.

These registers were accessed by variants of the MOV instruction.